[libre-riscv-dev] [hw-dev] Re: 6600-style out-of-order scoreboard designs (ariane)

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed May 15 18:15:16 BST 2019

On Wed, May 15, 2019 at 5:50 PM Mitchalsup <mitchalsup at aol.com> wrote:

> Looking at your schematic you sent, I comes to mind that the paths seem too long.

 yes, ok, so yosys graphviz schematics take a little getting used to:
latches are "loops", and anything else is just "renaming
opportunities".  new names for NETLISTs basically, due to inputs from
one module being the outputs used in another.  these name-changes can
be safely ignored.

 i'll redo a new (updated) schematic tomorrow, i've gone back to the
FU-only approach, am having better luck with it.  however i need to do
a big tidyup as it's a bit of a mess.

> You should have a block where on one side you get input signal vectors {Issue__FU,
> Go_Read_FU, and Go_Write_FU} These propagate through the SB and create the
> output vectors {FU_Busy, Readable, Writeable}.

 got this.  Readable is the subject of a post just now on hw-dev (soon
to be libre-riscv-dev)

> A Picker, then, selects the Readable
> vector and create the Go_Read vector which is flopped.

done.. wait... this is inside the FU?

> At the same time another
> picker selects the Writeable vector and creates the Go_Write vector.

 got that.

> Transitively, the Go_Write vector deasserts FU_Busy enabling Issue.

 got that.

> I see this as 3 paths each being a small number of gate delays; 2 paths of which end up
> at 1 gates of delay pickers (1:4 pickers), the other end up at FU_Busy.
> Mitch Alsup
> MitchAlsup at aol.com
> -----Original Message-----
> From: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> To: Mitchalsup <mitchalsup at aol.com>
> Sent: Wed, May 15, 2019 11:08 am
> Subject: Re: [hw-dev] Re: 6600-style out-of-order scoreboard designs (ariane)
> On Mon, May 13, 2019 at 8:53 PM Mitchalsup <mitchalsup at aol.com> wrote:
> > I might suggest that you drop back and get the FU-Reg working first without any additions
> > and then add in the additions making sure they don't screw anything up.
> i went back to the augmented FU-only approach, and managed to get it
> working by making some minor alterations.  i'll post on-list.
> btw can i ask if it's ok to transfer the conversation to
> libre-riscv-dev, which is the list dedicated for the project that i'm
> doing? I have no objection.
> l.
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