[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=44

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #17)

> > err... the paper does say -1, 0 or +1 (as does Tanako), this will need
> > to be checked.
> yeah, it is -1, 0, or 1. I had meant that -1 in 2s complement is 0b11, not
> 0b10.

yes, very strange. will need to see what happens on implementation.

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