[libre-riscv-dev] latch/register helper routine
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat May 11 05:23:56 BST 2019
as it is needed in 4 places in one file, i created the following, added to
+def latchregister(m, incoming, outgoing, settrue):
+ reg = Signal.like(incoming) # make register same as input. reset is OK.
+ with m.If(settrue):
+ m.d.sync += reg.eq(incoming) # latch input into register
+ m.d.comb += outgoing.eq(incoming) # return input (combinatorial)
+ with m.Else():
+ m.d.comb += outgoing.eq(reg) # return input (combinatorial)
it's a really simple helper routine that creates a register to match its
incoming "thing". if the condition "settrue" is asserted, a copy of the
"thing" is made (for subsequent use on subsequent clock cycles), and in
*this* clock cycle, the "thing" is *also* passed through to the output.
if the condition is NOT asserted, then the output is set to the OLD copy
(which had been "conveniently" set on prior clock cycles).
yosys nicely turns this into a MUX and a DFF (attached), which is precisely
what's needed. the MUX allows the output to go *back* into the input of
the DFF (sustaining it indefinitely... hence this is a register), and if
the MUX is ever "asserted", the new value is switched in and will become
the value of the register on subsequent cycles.
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