[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=44

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://codestall.org/2017/06/26/carry-save-adder/

module csad(
output [7:0]s,
output co,
input [7:0]a,b,
input ci);
wire c1,c2,c3;
wire [3:0]s1,s2;
rcad u1(s[3:0], c1, a[3:0], b[3:0], ci);
rcad u2(s1, c2, a[7:4], b[7:4], 1’b0);
rcad u3(s2, c3, a[7:4], b[7:4], 1’b1);
mux4b_2_1 u4(s[7:4], s1, s2, c1);
mux2_1 u5(co, c2, c3, c1);
endmodule

module mux4b_2_1(
output [3:0]y,
input [3:0]a,b,
input c);
assign y = c ? b : a;
endmodule

module mux2_1(
output y,
input a, b, c);
assign y = c ? b : a;
endmodule

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