[libre-riscv-dev] [Bug 81] implement 6600-style "precise" out-of-order scoreboard

[Luke Kenneth Casson Leighton]

as people have probably noticed, i started (just because i can) to
implement mitch alsup's book chapters, turning all of the various
diagrams into nmigen modules.  with mitch's help, it's going well.

it is really surprisingly straightforward, and should take care of all
the things that make a standard in-order design really hairy:
load-pipeline stalls, tricks associated with interrupt masking,
awkwardness over branch prediction, all taken care of: the fact that
we can get huge parallelism out of it by throwing more pipelines and
more register ports in is just an accidental beneficial side-effect.

what i particularly like is: precise exceptions and other damage to
the register file or to memory is all taken care of through "shadow"
wires (nicknamed "schroedinger wires... :) ) that prevent and prohibit
writes... but *still let results be generated*.... they're just not
permitted to be written until it is *known* that the exception (or
other potential damage) cannot occur.

what it doesn't do is: cover the decisions on what constitutes a LD/ST
clash: this is similar to the rules for SFENCE, and in many ways
SFENCE i believe actually becomes irrelevant because the augmented
6600-style scoreboard is capable of detecting exactly the conditions
for which SFENCE was designed.

anyway... still lots to do...

l.