[libre-riscv-dev] 53000 as ME for libre-riscv - bus interfaces?

[Samuel Falvo II]

On Sat, May 4, 2019 at 8:32 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>  ok, so that would mean not being able to work within the nmigen
> simulation environment: it would be necessary to compile nmigen to
> verilog, and use e.g. cocotb or other testing framework.

When building the Kestrel, I simulate individual cores.  But when it
comes to integrating multiple cores together, I test on the FPGA
itself, building small test harnesses if required.  The Kestrel's
design is simple enough that I can afford this as a reasonable
alternative to simulating the entire computer.

I came to adopt this approach back when I was building the first
Kestrel-2 (with my 16-bit stack CPU, the S16X4).  I was using the
Xilinx tools at the time, and simulated the whole computer (minus
video for practical reasons).  Everything looked to be working OK, but
when synthesized and uploaded to the Spartan 3, the design just
wouldn't work.  I was forced to debug it with my oscilloscope probing
various and manually exposed interior signals.  I've never changed my
approach since those days.

>  so, if you set TileLink as the sole exclusive bus, what are they

I wasn't planning on making TileLink the exclusive bus.  By providing
IFU, LD, and ST classes as parameters at the time you instantiate the
CPU, you should be able to make a tailored processor that fits your
interface requirements.  I envisioned something like this:

from cpu.lib.somewhere import wishbone, tilelink, axi4, axi3

INTERFACE=wishbone   # or tilelink, or axi4, etc.

m.submodules.cpu = KCP53000B(
    ifu=INTERFACE.IFU, ld=INTERFACE.LD, st=INTERFACE.ST,
    reset_pc=0xABCDABCC, ..etc..
)

where "iface" would be a Python module of your choice imported earlier
(e.g., wishbone, tilelink, axi4, whatever).

> if however it is written in nmigen, and uses AXI4, there is this:
> https://github.com/peteut/migen-axi

I am under the understanding that migen and nmigen are not source
compatible with each other.  Am I mistaken?

That said, when looking at that repository, I have to admit that my
relatively inexperienced eyes do not see anything which I could
possibly reuse in my design.  If I wanted to support axi4, I'd have to
start from scratch (perhaps using migen-axi as a template to work
from).  I've /never/ found a prepackaged bus interface repository
which I could just drop-in and use as-is.

The closest I've been able to find to that ideal for re-use is this:
https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/heavycomps/heavycomps
, but even this would require customization for my specific project.

(I'm glad to have googled that, because it shows me how to use
Records, which I've been baffled over for some time.  Bookmarked for
future nmigen documentation.)

-- Samuel A. Falvo II