[libre-riscv-dev] Introduction

[Samuel Falvo II]

Since my target application is a home computer environment, good (even if
not best in class) performance is a requirement.

On Thu, May 2, 2019 at 8:04 PM Jacob Lifshay <programmerjake at gmail.com>
wrote:

> On Thu, May 2, 2019, 19:44 Samuel Falvo II <sam.falvo at gmail.com> wrote:
>
> > On Thu, May 2, 2019 at 5:38 PM Luke Kenneth Casson Leighton <
> lkcl at lkcl.net
> > >
> > wrote:
> >
> > >  is that... are you storing *only* the modifiable bits, to save gates?
> > >  if so, cool!
> > >
> >
> > I am indeed.  That's one of my beefs with the priv-spec as it's currently
> > written; so many registers have WPRI fields, and I'm just baffled as to
> why
> > we need the vast majority of mstatus to be garbage/scratch register
> space.
> > Considering the sheer importance of mstatus, I'd expect that it would be
> > mostly hardwired values if a bit field isn't supported.  I look at things
> > from an FPGA perspective, especially those which Yosys tools can target,
> > which are not that large.  Both LCs and DFFs are at a premium.
> > Implementing the 53000B on an iCE40HX8K is going to be my greatest
> > challenge, I think; the CSRU already takes up 1/6th the chip's resources.
> > :(
> >
> If you don't care about performance, try a bit-serial implementation, it
> should reduce the logic required by quite a bit, also, assuming it's like
> xilinx fpgas, the sram in a lut can be used as a 16 or so bit shift
> register, allowing you to use much less space.
>
> For an interesting bit-serial computer, see /Patterns/WireWorld/primes.mc
> in Golly http://golly.sourceforge.net
>
> I actually designed my first computers in Golly, rather than using a more
> traditional method.
>
> Jacob
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-- 
Samuel A. Falvo II