[libre-riscv-dev] buffered pipeline

[Jacob Lifshay]

implemented rc4, but I'm getting a test failure, will debug in the morning

On Wed, Mar 20, 2019 at 11:36 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Thu, Mar 21, 2019 at 5:33 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > >  ? que? you've lost me.  can you clarify: are you saying that you're
> > > concerned that the python random library does not have sufficient
> > > entropy?
> > >
> > I'm concerned that we won't be able to have multiple independently
> > advanceable sources of exactly reproducible pseudo-random numbers that
> can
> > be used on a fpga for testing.
>
>  ok.  well, one solution to that is to pre-compute the random numbers,
> store them in memory (or a file).
>
>  also, python's random library has a "seed" function, which sets the
> PRNG state to a reproducible sequence.
>
>  on an FPGA... potentially filling in some of the reasoning, here:
> you're thinking in terms of having a suitable PRNG on the FPGA, and
> the unit tests being uploaded into the FPGA as well?
>
> > NON-cryptographic. I know RC4 is essentially broken as a crypto
> primitive,
> > I'm just using it because it is close enough to a perfect source of
> > randomness for simulation and testing purposes, and it's really simple.
>
>  cool.
>
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