[libre-riscv-dev] buffered pipeline

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Wed, Mar 20, 2019 at 10:32 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

>  once that's done, the end result is that the MetaStage class instance
> would simply be passed in to one single Pipeline instance: end result,
> only one clock cycle.

 untested, looks like this, below.  could reaaally have done with this
several weeks ago.  and with having the whole concept of inspec and
outspec.  i'd made an attempt in the FPU code at identifying input
*variables* and output *variables*: it hadn't in any way occurred to
me at the time to identify the *types* of the input and output
variables.

class StageChain:
    """ pass in a list of stages, and they will automatically be
        chained together via their input and output specs into a
        combinatorial chain.

        * input to this class will be the input of the first stage
        * output of first stage goes into input of second
        * output of second goes into input into third (etc. etc.)
        * the output of this class will be the output of the last stage
    """
    def __init__(self, chain):
        self.chain = chain

    def ispec(self):
        return self.chain[0].ispec()

    def ospec(self):
        return self.chain[-1].ospec()

    def setup(self, m, i):
        for (idx, c) in enumerate(self.chain):
            if hasattr(c, "setup"):
                c.setup(m, i)              # stage may have some module stuff
            o = self.chain[idx].ospec()    # only the last assignment survives
            m.d.comb += eq(o, c.process(i) # process input into "o"
            if idx != len(self.chain)-1:
                i = self.chain[idx+1]      # becomes new input on next loop
        self.o = o                         # last loop is the output

    def process(self, i):
        return self.o