[libre-riscv-dev] buffered pipeline

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Mar 19 12:30:28 GMT 2019


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On Tue, Mar 19, 2019 at 11:06 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> > so, you mean it has multiple ready/valid inputs
>
>  with associated data on each, plus a selection strategy

https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/nmigen_add_experiment.py;h=6adbc2f85d16da0a9d6f1016808fbb1b1e990815;hb=dd44faf5abdf0205aa35c3a774ea60d8467e8e7e#l103

> answer: a hybrid of both, however the hybrid may be done by having
> multi-bit "ready" signals that must be all 1s before allowing to
> proceed.

 https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/nmigen_add_experiment.py;h=6adbc2f85d16da0a9d6f1016808fbb1b1e990815;hb=dd44faf5abdf0205aa35c3a774ea60d8467e8e7e#l48



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