[libre-riscv-dev] TLB key for CAM

[Daniel Benusovich]

I tested it yesterday and the default behavior was pass through. So we are good.

Otherwise it would be the end times indeed.

On Tue, Mar 12, 2019 at 11:50 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> On Wed, Mar 13, 2019 at 5:17 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > On Tue, Mar 12, 2019, 22:14 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > wrote:
> >
> > > ---
> > > crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> > >
> > >
> > > On Wed, Mar 13, 2019 at 4:58 AM Daniel Benusovich <
> > > flyingmonkeys1996 at gmail.com> wrote:
> > >
> > > > >  the example is of a RegisterFile.  i mention it because you created
> > a
> > > > > class called RegisterFile and it uses an Array rather than a Memory
> > > > > class.
> > > >
> > > > Woops
> > > >
> > > >
> > > :)
> > >
> > >
> > > > >  the reason for using the Memory class is because the Memory class is
> > > > > specifically designed to map down to verilog arrays / array indices,
> > > > > which in turn are fully and properly recognised by synthesis tools to
> > > > > map to SRAMs and ported memory, both on ASIC tools as well as FPGA
> > > > > synthesis tools.
> > > >
> > > > Makes sense to me. I will delete my existing RegisterFile and use a
> > > > memory block instead. Should I use the RegisterFile from the example?
> > > > It seems so nice.
> > > >
> > > >
> > > if it works and does the job, go for it.
> > >
> > > btw one other requirement: pass-through on the register file. i.e. the
> > data
> > > being written is available *immediately* - on the *same* clock cycle - if
> > > read.
> > >
> > If it can't do that, we can use a bypass mux and a address compare unit.
> > for byte-level write enables, we can have the mux be controlled on the byte
> > level.
> >
> >
> https://m-labs.hk/migen/manual/fhdl.html?highlight=memory#memories
>
> it seems to be the case that the option "synchronous" needs to be true
> (which is the default), and the mode set to WRITE_FIRST (which is also the
> default).
>
> so i *think* the default behaviour is what will be expected.
>
> also, the "granularity" argument is the number of subdivisions of the
> memory width, resulting in multiple write-enable lines.
>
> there doesn't appear to be a migen-to-nmigen compatibility layer for the
> Memory class, so the arguments are slightly different from the migen 0.8
> manual.
>
> l.
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