[libre-riscv-dev] buffered pipeline
programmerjake at gmail.com
Wed Mar 13 08:45:04 GMT 2019
On Wed, Mar 13, 2019, 01:39 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Wed, Mar 13, 2019 at 8:27 AM Jacob Lifshay <programmerjake at gmail.com>
> > note that in my pipeline stage design, succ_accepting to pred_accepting
> > doesn't go through a flip-flop so it isn't delayed a clock cycle, meaning
> > that a stage can block all predecessor stages in a single clock cycle,
> > eliminating the need to have extra stage registers.
> > I didn't include the table in the email, but I did check all combinations
> > of succ_accepting, pred_sending, and data_valid and it works just fine.
> can you please write a unit test (which has the side-effect of creating a
> waveform as output) so that i can take a look?
sure, I'll do it in the morning though. I had just checked the truth table
by hand when writing the email.
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