[libre-riscv-dev] buffered pipeline

[Luke Kenneth Casson Leighton]

https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html

i experimentally-implemented the above buffered pipeline, here:
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/example_buf_pipe.py;h=b72e1c43904451ba0ef7f9fa78d5417da8de0a8d;hb=0e70fec7c3df1ee97020aa5be6f358c85898a5fb

it is... very confusing.  the names stb/busy, there are pairs: input
and output, however the connection for previous and next is crossed.

in the john dawson code, the stb / ack signals act effectively as a
clock.  you *must* raise and then lower the "ack" signal each and
every time that data is ready, and the sender will *not* initiate a
new data send until it has seen that raise *and* lower.

this means that the john dawson code's data receive and transmit rate
is *half* that of the clock.

by contrast, dan gisselquist's code is designed to keep on receiving
(or transmitting) data on every clock, for as long as stb is true and
busy is false.  it also seems to cope with all the situations such as
when input is ready and output is not (this activates "store incoming
data in buffer") and allows the stage to tell the input to stop
sending any more data (without losing the *current* data).

there may however be a bug in what dan has published:
if (!o_stb)
   o_data <= i_data;

i believe this should be "r_data <= i_data" according to the comments,
given that it says "store incoming data in temporary".

insights and comments appreciated.

l.