[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

[Luke Kenneth Casson Leighton]

i've made a start on an "InputGroup" module which is the front-end of
what mitch alsup terms a "concurrent computation unit".  the idea is,
to put an array of input latches for the input operands and a
corresponding array of output latches for the results onto a single
pipelined ALU.

the minimum array width of the input-output latches has to be equal or
greater to the pipeline depth, otherwise it's pretty much a complete
waste of time having the stages of the pipeline.  sometimes however
that's unavoidable, such as for DIV operations where the completion
time will be extremely long.

the InputGroup module has an array of pairs of operands as input and
has a single pair of operands as output, plus a "Mux ID" which is the
array index of the operands that are ready.

i spent last week putting in the exact required "Mux ID" into the
FPADD module, ready for this, so that the Mux ID, when received from
the InputGroup, can be passed through the pipeline, and will come out
the other side so that it can be used to identify the correct output
in the Output Latch Array.

this identification is essential for a variable-length pipeline with
early-out capability (which is what FPADD, FPMUL and so on are, with
the Special Cases logic being able to jump out).  it's also a
complication as potentially two results may be ready in a given cycle,
i'll deal with that when it comes to it.

btw just to reiterate (jacob?), if there is only one ALU and it
arranged with this structure surrounding it, it becomes a single-issue
in-order design.  in such an in-order design, the array of
input-output latches helps deal with the early-out capabilities of any
pipeline.

l.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 2019-03-11_09-40.png
Type: image/png
Size: 14874 bytes
Desc: not available
URL: <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/attachments/20190311/f353d5ae/attachment-0001.png>