[libre-riscv-dev] Wish to work on

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Sat, Mar 9, 2019 at 6:37 AM Rishabh Jain <rishucoding at gmail.com> wrote:
>
> Luke, how do you cut verilog file for only one module?

with a text editor.

> Do you create a separate file containing only
> the top module?

 yes.

>
>
> Daniel, I followed your message:
>
> 1. I see, new modules: AddressEncoder, Decoder, VectorAssembler, etc have
> been added when i run
> read_verilog Cam.v
>
>
>
> 2. I got the dot file graph. " show top "  does work. thanks !

 oh!  i wish i'd known about that a looong time ago :)

l.