[libre-riscv-dev] Wish to work on

[Daniel Benusovich]

> I get a error message when I do "yosys > show" :

When you run the yosys command "read_verilog Cam.v" the application
creates a separate visual representation of each sub module present in
the design as well as the main module "top".

By executing "yosys show" without selecting a module the output error:
> ERROR: For formats different than 'ps' or 'dot' only one module must be selected.
is saying you have not actually not selected anything to be displayed.
Makes sense that it can display that! It took me a bit to figure out
and some serious tab tapping.

So, to actually display the graphs I found that this order of commands
works nicely.
1. Navigate to the src directory (make sure you are up to date)
2. execute "make"
3. execute "yosys"
  This should open the application yosys in the terminal
4. execute from inside yosys "read_verilog Cam.v"
  The command line should look like "yosys> read_verilog Cam.v"
  This should read all of the verilog in Cam.v and display the
following onto the terminal
  > Executing Verilog-2005 frontend.
  > Parsing Verilog input from `Cam.v' to AST representation.
  > Generating RTLIL representation for module `\anonymous'.
  > Generating RTLIL representation for module `\anonymous$1'.
  > Generating RTLIL representation for module `\anonymous$2'.
  > Generating RTLIL representation for module `\anonymous$3'.
  > Generating RTLIL representation for module `\decoder'.
  > Generating RTLIL representation for module `\encoder'.
  > Generating RTLIL representation for module `\p_encoder'.
  > Generating RTLIL representation for module `\top'.
  > Successfully finished Verilog frontend.
5. execute "show top"
  You could also execute "show encoder" or "show anonymous" (which is
one of the CamEntry modules).

Note that I will probably be consolidating some items into modules
such as the encoders into a single module. So it may change what is
displayed. Hopefully this gets you a nice graph displayed.

Cheers,

Daniel B.

On Thu, Mar 7, 2019 at 7:54 PM Rishabh Jain <rishucoding at gmail.com> wrote:
>
> "yosys > read_verilog Cam.v" runs fine, console log ends with
> "Successfully
> finished Verilog frontend".
>
> I get a error message when I do "yosys > show" :
>
> "2. Generating Graphviz representation of design.
>
> ERROR: For formats different than 'ps' or 'dot' only one module must be
> selected.
> "
>
> But, "yosys > show -format dot " this works fine: ends with "Dumping
> module
> anonymous to page 8"
>
>
>
> Then, linking the python3.6 binary with python3 works. Now, python3
> invokes
> python3.6 binary. Thanks!
>
>
>
> I was able to observe the waveform.
>
> I tried to right click on "top" (position is left top side in my case), but
> not option were coming.
> Though, I was able to load all the signals by "Search -> Signal Search
> Hierarchy
> -> select 'top' and insert"
>
>
>
> Yes, the waveforms are pretty clean and clear.
>
>
>
> Yep, I have cocotb installed.
>
> Now, i guess the tools are working fine.
> can you share the specifications for TLB and CAM which we intend to
> develop?
>
>
>
>
> On Thu, Mar 7, 2019 at 2:49 AM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > On Wed, Mar 6, 2019 at 5:18 PM Rishabh Jain <rishucoding at gmail.com> wrote:
> > >
> > > Thanks for welcoming me :)
> >
> >  :)
> >
> > > I have read the charter and found it very sensible. I will obey the "Code
> > > of Honour".
> >
> >  it's just... it feels totally different, doesn't it? a code of
> > "conduct" is an imposition: a demand for external restriction of
> > behaviour.  a code of "honour" is something that *you* take
> > responsibility for (and pride in).
> >
> > > For installing yosys and nmigen:
> > > I have cloned the *yosys* repo from https://github.com/YosysHQ/yosys and
> > > ran make, make tests and sudo make install.
> > > And cloned the repo of *nmigen* and installed using " pip install git+
> > > https://github.com/m-labs/nmigen.git "
> > > These tools look interesting.
> >
> >  yeah, they are.  yosys can actually be used to generate netlists for
> > ASIC layout, as well as for FPGAs.
> >
> > > In the soc/TLB/src directory: I changed python3 to python3.6 in Makefile.
> > > After doing make, I got this console log : "python3.6 Cam.py generate -t
> > v
> > > > Cam.v"
> >
> >  ok great: now you have a Cam.v file, run yosys and do this:
> >  $ yosys
> >  yosys> read_verilog Cam.v
> >  yosys> show
> >
> >  you *might* need to install xdot to get that to work properly
> > (apt-get install xdot)
> >
> > > In my computer, python3 default is set to 3.5 version. I looked into
> > > modifying this:
> > >
> > https://askubuntu.com/questions/900493/how-to-change-python3-from-python3-5-to-python3-6
> > > But, I fear my system will break. So, better I will manually call
> > > python3.6.
> >
> >  ok you can "fix" that in any given window, like this:
> >
> >  mkdir ~/socbin
> >  ln -s /usr/bin/python3.6 ~/socbin/python3
> >  export PATH=~/socbin:$PATH
> >
> >  that last line, you can put into a file somewhere, which you can do
> > "source {filename}"
> >
> > > Luke, can you give me an overview/brief on the 'soc' repository?
> >
> >  well, it's really basic at the moment, and will expand later.
> > there's only really 2 main directories: TLB/src which contains the
> > modules that daniel's been working on, and TLB/test which contains the
> > unit tests.  you can experiment with them like this:
> >
> >  $ cd TLB/test
> >  TLB/test$ mkdir Waveforms
> >  TLB/test$ python3 test_cam.py
> >  TLB/test$ gtkwave Waveforms/test_cam.vcd
> >
> > (obviously, apt-get install gtkwave first)
> >
> > then you can right-click on "top" on the right side, and
> > recurse-import all the signals.  then hit the "zoom fit" button and
> > you'll see all of the signals and when their values change, on
> > different clock cycles.
> >
> > honestly it's pretty damn cool and it makes me wonder why the heck
> > it's not more commonly available as a standard python software
> > debugging tool!  being able to sequentially visualise *all* of the
> > variables of a program as it progresses line-by-line would be
> > extremely useful!
> >
> > anyway if you left click anywhere on the main window you'll see a red
> > line, and then the values in the middle pane will change and you'll
> > see the values of all signals at that point.  you *may* need to scroll
> > the middle pane to see them.
> >
> > basically that gets you "up and running" and confirms that all of the
> > debug and dev tools are operational.  hey do you still have cocotb
> > installed btw?
> >
> > l.
> >
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