[libre-riscv-dev] building a simple barrel processor

[Luke Kenneth Casson Leighton]

On Fri, Mar 8, 2019 at 6:11 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> Just to clarify, I'm asking if you think it's a good idea to work on this
> since it will take some time.

 at its heart a barrel processor is a single-core single-issue
timeslicing design, suited to real-time I/O processing.  if we were to
add multiple barrel 4-time-sliced SMP cores, it would result in
multiple proliferations of the massive dual/triple-ported 8k SRAMs.

i just don't believe that a barrel processor will yield a useful
design for a production quality 6 GFLOPs SoC within the required power
budget, which is the target at which, if met, i can go back to the
client and say "we met the target, how about that $100k".

also, there's someone whom i'm encouraging to introduce themselves who
would like to help with the OoO implementation, they're getting
settled in having just moved house.  they've got prior experience with
OoO.

l.