[libre-riscv-dev] building a simple barrel processor

[Luke Kenneth Casson Leighton]

On Friday, March 8, 2019, Jacob Lifshay <programmerjake at gmail.com> wrote:

> .
>
> I think I could get a decently working prototype in a few weeks.
>
> If it has a good enough design and we end up wanting to go with a barrel
> processor, we could use it as a base design for our gpu.
>
> Comments?


According to the wikipedia page barrel processor is a uniform non stallable
pipeline with a limited extremely uniform single issue form of
hyperthreading.

It works by requiring complete copies of the register file, PC, (and most
likely the entire CSR State as well) which are then "barrelled" on uniform
timeslices.

For the GPU that will include the entirety of the SV state.

The key here is that we have 256 64 bit registers. Copying that will be
MASSIVE.

This is a known downside of a barrel processor design, which has more
severe consequences for us than a standard processor.

The main deployment scenario for barrel processors is for real time
guarantees that the timeslicing brings. It appears to be typically deployed
for IO processors according to the wikipedia page, which makes a lot of
sense.

However for our needs, I am not perceiving any advantages for a GPU
deployment, I can however see an advantage to using a barrel processor for
softcore bitbanging implementation of peripherals such as SDMMC , SPI, I2C,
Parallel CSI and so on, which I had considered raising at some point, now
being as good a time as any.

One particularly important aspect of the barrel is that the core's cycle
rate is DIVIDED amongst the hardware threads. A 1ghz clock with 4 hardware
timesliced threads would not only have only 250mhz each, we would have an
absolutely staggering 1024 64 bit registers.  That's 8k worth of ported
SRAM, plus additional multiplexers.

The benefits for resistance to timing attacks are, I feel, more down to the
inherent requirement for uniform timeslicing, typically required for IO and
realtime scenarios. It's not the actual barrel itself that produces the
resistance.

All that having been said, whatever start is made on any design will be
time well spent. For example the instruction decode section will be needed
no matter what, the CSR declarations likewise.

L.


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