[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Sat, Mar 2, 2019 at 4:12 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:


> so it's a leeetle complicated, and i want to get through this first
> hurdle (which worked, this morning).  actually, it's a lot
> complicated, i'm constantly having to throw away and back out of
> modifications that keep failing.  now that i've got normalisation
> working on a multi-cycle basis, i can continue removing dependence on
> global variables.

 almost all done, now.

> in the meantime, yes, the overflow complication needs to be thought through.

 suddenly occurred to me, real simple: just re-append the 3 bits
(guard/round/sticky) back onto the result, perform the shift, then
split them back off again.

 i already have a function which can do the right-shift and also take
the bits being dropped and merge them into the "sticky" bit.  it has
to be done dynamically, so there's two rshifts: one taking
"0b11111111111111111" as input that is shifted by (width-expdiff) as a
mask, then &'d with the mantissa, and tested for any bit in that being
1.

there's probably a better way to do that.

l.