[libre-riscv-dev] IEEE754 FPU

[Jacob Lifshay]

On Fri, Mar 1, 2019, 17:04 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> Ok so I am making a complete pig's ear of the adder, slowly and painfully
> transforming it to connect inputs to outputs instead of taking global
> variables and extracting and dropping the stage data in and out of globals.
>
> Each stage's logic I have split out into combinatorial module blocks with
> input and output, no clock sync at all. This is deliberate so that it
> becomes possible later to combine phases into a single cycle, reducing the
> number of "states" and also when doing pipelines reducing the number of
> pipeline stages.
>
> The chain has a bypass on the add and normalisation, due to special cases
> for zero, NaN and Inf, however the use of global variables made it
> complicated to split the chain. I suceeded by creating a new state that
> puts the intermediate z from the add stages into the output, separate from
> a different z used to store the special cases, these two different stages
> go into the same output.
>
> This separation allowed me to remove at least one global variable.
>
> The normalisation phase is currently the biggest hurdle as it is a
> multi-cycle phase. My next efforts will be to work out how to get the
> normalisation phase to cycle on an internally protected local temporary
> variable, only outputting it when the result is ready.
>
you could change normalization to a count-leading-zero operation combined
with a left shift. That would make it take 2 operations instead of a
variable number.

>
> The problem right now is that the data from the normalisation phase changes
> AFTER it is suppised to be finished.
>
> Still working on it.
>
> L.
>
>
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