[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

[Luke Kenneth Casson Leighton]

Ok so moving on to scalar-vector, in SV original, a bit in the CSRs
specifies whether the register is scalar or vector, and 2 more bits specify
the elwidth override.

When elwidth is overridden, even for scalar ONLY the parts of the physical
regfile up to the elwidth are read (or written).

So if elwidth is 8, only the LSByte of the regfile record for that register
is read/written.

If however elwidth is default, and LD.B is used, you get the standard
behaviour: 1 byte read but it is zero-extended to 64 bits.

We need some rules for SVprefix, in the extremely limited available bits.

We so far agree that 1 bit be used as a prefix to regnums. 0 means scalar,
can't recall if that means x0-x31. 1 means vector, with bottom 2 bits being
0 and next 5 bits being the rs/rd 5 bits.

Elwidth to be taken from standard RV OP, no problem there.

However we need to define whether the scalar elements should be zero/sign
extended or if they should be compressed together, and likewise for vector.

Or, if that extra elwidth bit (or two) is needed.

What I would like to advocate is that scalar regs not be altered, whether
src or dest, from standard RV behaviour.

And that it is Vector regs (when the reg prefix bit is 1) that have the
altered width behaviour.

So, a FP16 FADD of a prefixed-scalar to a vector would, if stored in a
scalar x1-x31, result in NaN boxing to the full 64 bits, however if the
dest was a Vector it would NOT be boxed, only the actual FP16 would go into
the regfile, NOT setting an additional 48 bits to all 1s.

Thoughts?


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