[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jan 31 03:34:28 GMT 2019

ok so i thought about the vlpN concept, and if the register-prefixing
encodes scalar/vector already, then reserving '0b00 for "scalar" is
redundant.  it would therefore be better to split out VL from
predicate specs.

there is however a small problem with VL multipliers: they break the
Vectorisation Loop paradigm, turning it effectively into a SIMD-like
one instead.

i am slightly concerned that the templates for VL-based loops would
need to be much more complex (less uniform), as the multipliers now
need to be taken into account within the loop, on a per-instruction
basis instead of a per-loop basis.


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