[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

[Luke Kenneth Casson Leighton]

On Monday, January 28, 2019, Aleksandar Kostovic <
alexandar.kostovic at gmail.com> wrote:

> >
> > you forgot rs2. some ops (shift, mulhsu, sub, div, mod, etc.) are not
> > commutative, so it'd be nice to have both scalar<<vector and
> > vector<<scalar.
>
>
> So you are suggesting that we should builds custom op codes that take like
> a range of scalars and turn it into a vector and opcodes that take vectors
> and broke it down into scalars?
>
>
We are endeavouring to avoid making any custom ops except where absolutely
strictly necessary.

One area where we have identified a missing necessary op is MVX - regs(rd)
= regs(rd + regs(rs)). Or minor variants on that, at least.  MVX does not
exist in Standard RV, and it is extremely hard to implement (lookup table
or self-modifying code).

The idea is to make it possible for present *and future* 32 bit opcodes to
fit into a 48bit space, where the free bits "prefix" the 32 bit op to make
it a parallel one.

The problem is, due to the way that 48bit encoding is designed in RISCV, we
only have 12 bits to play with.

Sorry if this has been asked before, but i am trying to grasp all the
> things right now.


No problem. Jacob and I have been exploring this particular investigation
for a couple weeks now.



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