[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

[Luke Kenneth Casson Leighton]

On Sat, Jan 26, 2019 at 2:17 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Saturday, January 26, 2019, Jacob Lifshay <programmerjake at gmail.com> wrote:
>>
>> > Really, I prefer 2 for 32bit int ops and all C ops, that way it's always
>> > possible to specify 8/16/32/default.
>> >
>> 32-bit int ops can have a single bit that switches from 32/default
>> (OP-32/OP) to 8/16.
>
>
> I know there is something odd with the OP32 stuff in RISCV, it was discussed a year ago. The opportunity to have RV32 executables run unmodified on an RV64 host (in RV64 Mode) was lost because the opcodes actually change meaning depending on whether RV32 or RV64 Mode CSR is set.
>
> I would feel comfortable with only a single bit to set 8/16 to OP32 / OP only after doing a full walkthrough.

 ok as i suspected, there is no direct equivalence between OP and
OP32.  the [flawed? pragmatic?] assumption in RV is that nobody would
want to seriously implement a hybrid RV32 *and* RV64 system in the
same chip.  if there are 64-bit registers, you do the calculations in
the entirety of the 64-bit space.

 consequently there is no OP-32 "AND", or shift, or SLL opcodes, and
likewise for OP-IMM/OP-IMM32.

this was why i ended up allocating 2 bits for elwidth.

l.