[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

[Luke Kenneth Casson Leighton]

hiya jacob, ok so i had a couple of days to think.

my main concern about modifying encoding of RV instructions is that SV
then becomes a dead-end as far as wider adoption is concerned, due to
the violation of the rule that "no instructions shall need
modification to be made parallel".  people considering adopting SV on
custom (or future) extensions may not have the same operands or types
of operands / modifiers, and the lack of clarity and simplicity makes
them stay away.

also: if we create what is effectively a new encoding, we might as
well stop entirely on SV, and implement RVV plus some custom
RVV-xBitManip extensions.  it would be a lot less work, particularly
software-wise.

so, can we do a parallel track (not *stop* the new encoding entirely),
seeing if it's possible to shoe-horn all the required prefixing into
the 12 bits *without* modifying the 32-bit encoding?  i like vlp4
(that's 4), i like the 2-bit scalar/vector-mod-2 idea (2+2 for rd and
rs*), that leaves 4 bits, at least 2 of which need to be allocated to
over-riding the dest-elwidth (as separate and distinct from the
*source* elwidth which comes from the operation).

that would leave 2 bits spare which could be used for more
operation-specific uses such as LD/ST behaviour.

what do you think?

l.