[libre-riscv-dev] TLB Initial Proposal

[Luke Kenneth Casson Leighton]

On Tue, Jan 22, 2019 at 6:52 AM Daniel Benusovich
<flyingmonkeys1996 at gmail.com> wrote:

> > We were specifically looking for ways to not need large CAMs since they are
> > power-hungry when designing the instruction scheduling logic, so it may be
> > a good idea to have a smaller L1 TLB and a larger, slower, more
> > power-efficient, L2 TLB. I would have the L1 be 4-32 entries and the L2 can
> > be 32-128 as long as the L2 cam isn't being activated every clock cycle. We
> > can also share the L2 between the instruction and data caches
> >
> Sounds great. Would the two levels of caching be separate types of memory
> entirely? For example, the first level is a CAM and the second level is a
> SRAM?

 don't know.  that security article tends to suggest that they are
both N-way.  in skylake the L1 TLB is 8-way and the L2 TLB is
TWELVE-way or something mad.

> What would determine the size of the caches? Would the cache size
> value be created through testing to see what gives the minimum number of
> misses vs power used?

 yyyep, pretty much.

> in the RISCV manual that for Sv48 implementation a 64 bit table entry is
> used for a 56 bit physical and virtual address. (Section 4.5.1 Figure 4.21
> pg. 64 V1.10)

 that's the one.

> So it seems that having a software controlled TLB with 2 levels of caching
> is the current course. Since misses will be handled in software what does
> need to be done in hardware? For instance, will fetching the translations

 software

> and placing them into the TLB

 hardware, with a special custom-designed instruction that
specifically targets the row in the CAM.

>  be a hardware or software task?

 a hybrid of both.

> If it is a
> software task then the TLB must accept certain instructions to do what it
> needs to or how does it work?

 design some instructions that treat the CAM as if it were "Yet
Another Register File" (aka "Memory Area").

job's done.

btw it will help you enormously to look at page 44 of mitch alsup's
2nd chapter, we have his permission to reproduce parts of it, with
credit.  i'm attaching a copy now.

basically we need:

* an exception to be raised that passes the address of the TLB "Miss"
* an instruction that allows updating of the box named "PTE"

err... job done!

oh, obviously, if we want a L1/L2 arrangement, there will be a 2nd
exception and a 2nd instruction.

l.
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