[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

[Jacob Lifshay]

On Tue, Jan 22, 2019, 03:04 Luke Kenneth Casson Leighton <lkcl at lkcl.net
wrote:

> On Tue, Jan 22, 2019 at 8:08 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > Changes to the proposal:
> > I changed where elmsz comes from in integer size conversions, using
> > OP-IMM/OP-IMM-32 to differentiate between unsigned/signed.
> > I split the elmsz mapping into elmszd/elmszw to allow reordering to match
> > the unprefixed sizes.
>
>  the thing about elwidth is that there needs to be one for the source
> operands and a *separate* one for the destination register
>
>  otherwise, explicit operations are needed which perform
> width-conversions.  which is feasible: special over-ride on MV / F.MV.
>
Width conversions are handled by conv for int to int, fcvt for fp to fp and
int to/from fp.

 also, how is vector-scalar and scalar-vector to be specified?
>
We will have broadcast instructions but may need to change the encoding for
the more common operations to accommodate vector-scalar modes for
power-efficiency and lower register pressure.
We could use the prefixed jal encoding as a different opcode for
vector/scalar as jal is useless when vectorized. We could also use the rest
of the space in BRANCH.
We could also use auipc, though that's handy for making pointers, so I'd
like to use other space first.

Jacob Lifshay