[libre-riscv-dev] TLB Initial Proposal

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Tue, Jan 22, 2019 at 9:07 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> The spec I was referring to is the RISCV manual. If all TLB misses are
> handled in software, we need:
> - the portion of the Physical Page Number that we implement (PPN)
> - the Virtual Page Number (VPN) along with a page size indicator
> (4KiB/2MiB/1GiB/0.5TiB)
> - a bit indicating readability (R)
> - a bit indicating writablility (W)
> - a bit indicating executability (X)
> - a user/supervisor bit (U)
> - a bit indicating if the page is global or local to an ASID (G)
> - the ASID (ASID)

 ah i forgot about these :)

> Note that we can change this algorithm, I just wrote it how I would do it.

 which is going to be critical to mitigating TLB timing attacks.

l.