[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Mon, Jan 21, 2019 at 10:23 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> I pushed a work-in-progress prefix proposal to
> https://salsa.debian.org/Kazan-team/kazan/blob/master/docs/Prefix%20Proposal.md

looks great;

elwidth

11 64-bit (d)

can you make that "default" (in both int & fp), so that:

 (a) when using the CSR tables, the "default" may be over-ridden
 (b) the elwidth can be taken from the opcode (and the usual
zero/sign-extension done: this is crucial for LD/ST)
 (c) RV32/RV64 mode can do the "normal" changing that is part of the RV spec.

the signed/unsigned table is not needed: i did a comprehensive
analysis as part of spike-sv which shows that the sign/zero extension
may be taken from whether the instruction has a ".W" suffix.  dead
simple.

the c.mv sign/unsigned: this makes me nervous (especially after
analysing how complex in the hardware it is to do).  it turns the
processor into a CISC design that effectively requires turning the
instruction into two microcode ops.  and it's element-based.

i would *really* really prefer that two *actual* instructions be used,
one to do the mv and the other to do the sign/unsigned conversion [or
that F.SGNetcetc be used].

> The prefixed C instructions are supposed to expand 1:1 to 48-bit
> instructions.
> Planning on filling in more later.

 ok cool.