[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

[Jacob Lifshay]

Working on a much more fleshed-out prefix proposal that supports using
32-bit instructions for common operations and expanding to bigger
instructions for the less common ones, allowing us to retain the
space/energy savings of the C extension.

On Sun, Jan 20, 2019 at 10:04 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> better at https://libre-riscv.org/3d_gpu/microarchitecture/#prefixes
>
> <pre>
> |           3      |           2      |           1      |           0
>   |
> | ---------------- | ---------------- | ---------------- |
> ---------------- |
> |                  | xxxxxxxxxxxxxxaa | xxxxxxxxxxxxxxaa |
> XXXXXXXXXX011111 |
> |                  | xxxxxxxxxxxxxxxx | xxxxxxxxxxxbbb11 |
> XXXXXXXXXX011111 |
> |                  | xxxxxxxxxxxxxxaa | XXXXXXXXXX011111 |
> XXXXXXXXXX011111 |
> | xxxxxxxxxxxxxxaa | xxxxxxxxxxxxxxaa | XXXXXXXXXXXXXXXX |
> XXXXXXXXX0111111 |
> | xxxxxxxxxxxxxxxx | xxxxxxxxxxxbbb11 | XXXXXXXXXXXXXXXX |
> XXXXXXXXX0111111 |
> </pre>
>
> bits available for different uses, and instructions that fit them:
>
> * 48b: 10 C C
> * 48b: 10 32-bit
> * 48b: 20 C
> * 64b: 25 C C
> * 64b: 25 32-bit
>
> 64-bit with 3 C instructions or 1C plus a 32 or a 32 plus 1C... too
> complicated.
>
>
>
> still thinking about these:
>
> 2x16-bit / 32-bit:
>
> <pre>
> | 9 8   | 7 6 5 |     4 3 |     2 1 | 0 |
> | ----- | ----- | ------- | ------- | - |
> | elwid | VL    | rs[6:5] | rd[6:5] | 0 |
>
> | 9 8 7 6 5 |      4 3 |   2 |   1 | 0 |
> | --------- | -------- | --- | --- | - |
> | predicate | predtarg | end | inv | 1 |
> </pre>
>
>
> y'know... we _could_ take over the entire RVV opcode space, to do a
> more compact way to set up the CSRs...
>
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