[libre-riscv-dev] Libre RISC-V Requirements Specification document

[Jacob Lifshay]

>
> > candidates that i can immediately think of include a L1/L2 SMP-aware
> > cache, a TLB table (virtual memory), a 64/32/16-bit IEEE754
> > Floating-Point ALU (or at least starting one) - there's probably
> > plenty of others that we can think of along the way (integer
> > multiplier unit for example, for compliance with the optional RV "M"
> > in "IMAFD").
>
I think that we can build a ALU that shares the integer and fp
multiplication circuitry, we would just need to implement a 64x64 bit
integer fma unit that can be partitioned to 2 32x32 fma units or 4 16x16
fma units. We should be able to share most of the circuitry by implementing
it that way, saving both power and area. We may want to include
partitioning all the way to 8 8x8 fma to support low-precision neural
networks. Each of the multipliers would need to support signed*signed,
signed*unsigned, and unsigned*unsigned.
I think it's a good idea to build in the extra shifters to support denormal
numbers without slowing down, also allowing us to avoid data-dependent
timing allowing the fma units to be useful for cryptography and mitigating
spectre-class bugs as well.
Notably, avoiding data-dependent timing means we can't short-circuit things
like Infinity/NaN or division. It also means that we don't need to have as
many pipeline stages that can write to the register file allowing us to not
need as many write ports.

Jacob