[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

[Jacob Lifshay]

I think that adding 16-bit instruction prefixes will be useful to encode
the high bits of the register numbers and extra bits for stuff like
selecting vectorization settings since those will change rapidly enough
that constantly writing to the rename table csrs may use more instruction
bandwidth.

The encoding I was envisioning will change depending on the underlying
instruction.

One of the important parts is that a prefixed 16-bit instruction fits in
the 32-bit custom space, a prefixed 32-bit instruction fits in the reserved
48-bit space, and a prefixed 48-bit instruction fits in the 64-bit space.
This allows them to not conflict with other standard/custom instructions
allowing any instruction to be prefixed.

For 32-bit underlying instructions, we can use the two lsb bits in the
underlying instruction that specify that the instruction is 32 bits as
extra bits:

0x00b5_0533 add x10, x10, x11
becomes
0x00b5_0530_001f add x10, x10, x11 with 12 available bits (some of which we
will need to leave constant for other uses of the 48-bit space).

I think we should use them this way:
2 for each of rs1, rs2, and rd to allow addressing 128 registers
2 for specifying a vl multiplier of 1x, 2x, 3x, or 4x
1 for selecting predicated/non-predicated with a fixed predicate register
of x9/s1 (in the range of rvc registers and not reserved for something else)
2 for:
    for 4 arg instructions like fma, 2 high bits of rs3
    for integer, selecting packed modes from 8-bit, 16-bit, 32-bit, and
64-bit
    we can pick something for other instruction types
1 as constant to allow other 48-bit instructions

We can come up with something similar for 16 and 48-bit underlying
instructions.

Note that we won't end up with the problems with SIMD always needing to add
more instructions since the list of element types isn't going to expand and
all of the instructions are vectorized with predication and variable vl.

The prefixed instructions would bypass the SV rename table since the prefix
specifies the high register bits and the predication.

Multiple prefixes in a single instruction are reassigned to operations like
reduction, packed type conversions, indexed/strided ld/st and others as
needed.

Jacob