[libre-riscv-dev] multi-issue predication

[Luke Kenneth Casson Leighton]

ok so the idea for simple-v was to use a multi-issue
micro-architecture, and for bits in the predicate that are zero,
simply... not issue an element-based vector instruction for that
specific element.

simple, right? :)

except... um... the predicate source register may not actually be
available at the time (it could still be being calculated by the
previous instruction), which completely throws a spanner in the works.

the solution that i propose is: we add a special "predication issue
decode Function Unit".  this unit (or, several of them), holds
*multiple* write-hazard "shadow" wires (plus multiple schroedinger
"Go_Die" wires), to be matched up one for *EACH* bit of the
predicate... *WHEN* the predicate becomes available.

so:

* the instruction which is currently calculating the register to be
used as a predicate raises a write-hazard against a
predicate-issue-decode FU
* the predicate-issue-decode FU *waits* for that register just like
*any other write-hazard FU*
* the predicated element-based instructions are allocated and made to
be dependent on the predicate-issue-decode FU
* those vectorised FUs *may* actually begin calculating their
element-based results, however they are *NOT* permitted to commit
those results
* once the predicate-issue-decode FU receives its src predicate
register, it farms out the bits one-by-one to the relevant
element-based FUs.
* if a predicate bit is ZERO, the corresponding "Go_Die" signal is
called on the FU dealing with that predicated (now cancelled) element
* if a predicate bit is ONE, the "write shadow" line is cancelled,
permitting that (predicated) element to proceed with writing to the
Register File.

the alternatives are a bit of a mess.  this is about as close as i can
get to something reasonably sane.

thoughts appreciated.

l.