[libre-riscv-dev] Migen Conversions and Update

[Luke Kenneth Casson Leighton]

Ok Daniel so would you like to take a look at nmigen, the code is quite
small, output v. tidy, you need latest yosys from git master. I really love
the "with" statement, see nmigen examples, ah we need to check that it can
generate a regfile, in migen there is a "memory.py" example which does all
the right things, including multiporting, passthrough of writes to reads,
and byte level write enable lines, i am unsure if that has been ported over
yet.

Jacob, about virtual regs table. VRegs table does not have to be unary, it
can be binary. However as unary it is automatically the "enable" lines on
each individual reg file memory cell, which is really nice.

Hypothetically this would mean independent simultaneous writes or reads to
each reg entry in one clock, however in practice it would mean 128 64bit
data buses and we aint doing that :)

If binary then that binary address has to be decoded inside the regfile
"box" itself. The unary matrix VReg to RealReg does away with that, so less
gates.

Also size of table not so bad as it is split to 4 banks and each 128 regs
get their own muxes. Remember, muxes are on src but not on dest.

Mitch Alsup did point out that line driving of 128 gates results in
significant latency, however our target is 800mhz certainly not 2 to 3 ghz,
also as it is driving unary encoders (128 mutually exclusive latches, only
1 of those may ever be set at any given time) it is really not as bad as it
initially looks.

I hope :)




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