[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Sun, Feb 17, 2019 at 8:31 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> Ok line 23 to 25, FPNum all need 2nd arg False, just like in div.py, this makes the mantissa 24 bit as opposed to 27 bit.
>
> 28, it is product not tot and it needs to be i think 51 bit.
>
> Indentation, 33 to 90 back 8 spaces, 91 back 4, 93 to 98 back 12.

 ok, you accidentally added a file from __pycache__, which is a binary
file.  what i've done is *REMOVE* that file *ENTIRELY* from the
repository, by REWRITING the git history.

 this means that you'll need to do a "git pull" followed by "git reset
--hard" to reset to a completely new "master" branch.  that's everyone

 please please don't do any commits until you've done the reset!  to
avoid that happening i've disabled write commit access temporarily,
and will put it back once i hear from everyone who has checked out
this code.

l.