[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Sun, Feb 17, 2019 at 8:25 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> >                     of.sticky.eq(div.quot[0] | (div.rem != 0))
> >                 ]
> >
> > does that look about right?
> >
> yeah, looks correct to me, though you can make the divider have one less
> quotient bit and just use div.rem != 0 for the sticky bit. You'd have to
> shift the indexes on div.quot down 1 bit as well.

 mmm... means actually having to understand what's going on :)

> may be best to leave the algorithm unchanged since this is just for demo
> purposes (from what I recall).

 yeah i know!  if everyone's ok with it we could revisit that?  if
it's feasible to use the various stages to create a pipelined variant.
i'd actually really like to try to keep the original "no-pipeline"
code around, and have 2 variants, particularly as we may *need*
non-pipelined variants of some of these.

> >  i have no idea how to do tininess or set odd/even rounding modes -
> > will definitely need your help, there.
> >
> ok. rounding modes are easy once you have the normalized number and guard,
> round, and sticky bits. will need to do more research on tininess.

 there's something in the IEEE754-1985 wikipedia page about
disagreements on tininess that didn't make it into the final standard
during draft development.

> >  i'm ok at this type of reverse-engineering-without-understanding,
> > however it turns out that i'm pretty much dyslexic when it comes to
> > algorithms.  i often substitute brute-force search through
> > permutations of and/or and off-by-one in combination with
> > seriously-comprehensive unit tests for "understanding" :)
> >
>
> for the final fpus, I'm going to try to use a theorem prover to prove the
> nmigen/verilog to be correct; no pentium-fdiv bugs for me!

 ha, cool :)

 of course... we couuld just do what intel does: have several teams
develop ALUs, and, rather than do what microsoft does which is to pick
the team that finishes first, put *ALL* of the ALUs in, by *ALL* of
us... oh and then have some logic which detects which ALU produced the
result in the least number of cycles and cancels the others :)

l.