[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Sat, Feb 16, 2019 at 11:27 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> suggestion, aleksander: do "diff -uwbB adder.v multiplier.v" and load
> that up into an editor (preferably one that does
> colour-syntax-highlighting on diffs).
>
> you can then make a copy of nmigen_add_experiment.py to
> nmigen_mul_experiment.py and *only* change the sections that are
> needed.
>
> don't start from scratch on the mul.py file, you'll take several hours
> longer than necessary.

 ... done with div :)

made a few errors (off-by-one in loops), it was by doing comparative
diffs on the verilog, and taking a copy of the add.py as a starting
point, i only had to replace the adder sections with divider sections.

i used the diff to *identify* the sections that needed to be replaced,
however i looked at divider.v to actually work out what to replace
those sections *with*.

also, i particularly had to watch out for the setup of the Latches a,
b and z, those are set up to be *24* wide, *not* 27-bit wide.

mul is the same, you can see that from the verilog diff ("diff -uwbB
adder.v multiplier.v")

-  reg       [26:0] a_m, b_m;
-  reg       [23:0] z_m;
+  reg       [23:0] a_m, b_m, z_m;

and:

@@ -84,8 +83,8 @@

       unpack:
       begin
-        a_m <= {a[22 : 0], 3'd0};
-        b_m <= {b[22 : 0], 3'd0};
+        a_m <= a[22 : 0];
+        b_m <= b[22 : 0];

so, you can see, in the FPNum decode function, i did this:

        args = [0] * (self.m_width-24) + [v[0:23]] # pad with extra zeros
        return [self.m.eq(Cat(*args)), # mantissa

that basically will do 3 LSB zeros if the width of the mantissa is 27
bits, but if it's *24* then the number of LSB zeros is *ZERO*, and you
get a straight copy of the value.

so, it means, you can just do this for FPMul:

    def get_fragment(self, platform=None):
        """ creates the HDL code-fragment for FPDiv
        """
        m = Module()

        # Latches
        a = FPNum(self.width, 24) << 24 not 27
        b = FPNum(self.width, 24) << 24 not 27
        z = FPNum(self.width, 24)

l.