[libre-riscv-dev] IEEE754 FPU

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Feb 15 13:07:51 GMT 2019


ok so this is really cool, i haven't put in anything particularly
special, just a few arbitrary numbers, and it seems to be working just
fine.  however... a "few tests" is nowhere near adequate.

interestingly, jon dawson has a test program.... written in python! :)
 it runs pipes to a c-based program that does a 32-bit FP add (10
lines of code), then compares the result against an
icarus-verilog-compiled testbench.

i'd really _really_ prefer that we tested against the softfloat
library, because its output is guaranteed independent of the OS, OS
bit width, and anything random and arbitrary (such as whether the c
compiler or the underlying hardware can do IEEE754).  also... not all
hardware has FP16.

be interested to hear everyone's thoughts.

l.



More information about the libre-riscv-dev mailing list