[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Fri, Feb 15, 2019 at 4:50 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> ok so next task: add in some tests, see if it works. i'll investigate
> how simulations are run in nmigen over the next couple days.

 HA! cool!  found a test online
https://m-labs.hk/migen/manual/simulation.html and adapted it, it's
actually really straightforward, and showing up bugs already.

 at the end, put_z state is not supposed to move back to get_a until
the user of the module acknowledges the output by setting out_z_ack.
that gives an opportunity to reset in_stb_a and in_stb_b back to zero.

 the subtract of 127 from the exponent.... it was being done at
bit-length of 7 *not* a bit-length of 10.  so i compensated for that
by adding 3 extra zero bits:

  self.e.eq(Cat(0,0,0, v[23:31]) - 127), # exponent (minus bias)

i'm now doing an add of 1.0 to 2.0 and getting the wrong result, am
investigating as the special-cases are skipping over and going
directly to put_z.


 very helpful, shows calculations in hex, binary and FP32 (click
binary32 at bottom) http://weitz.de/ieee/

l.