[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

okaaay, so time to take a look and see what the heck is going on.

you'll see i split out "pack" into a "corrections" and "pack" phase,
the reason for doing that is that i didn't like that the z output was
assigned *and* then corrected (Inf or -0 turned to +0), so what i did
was:

* split those out into a separate phase that alters the z.e (exponent)
and z.s (sign) contents.. *then*
* goes through to the "pack" phase which now does *not* alter the z
output with post-analysis, it *just* says "if overflow, set z=INF else
set z from s/exp/mant"

it's sort-of all making sense, if you focus on each state in turn.
aleksander, are there any bits that aren't clear, because that means
they need to be commented / reviewed.

l.