[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

ok so i'd previously stripped off the s_* from names, and you can see
out_z and friends, at line... 99, are members of the class.  unlike in
c++, python class members *must* be referred to with the prefix
"self." (equivalent to this-> from c++).

*local* variables (and global variables too) do not need "self."
because.. well.. they're local or global, respectively.

so... i *think* that's it.  the "reset" stuff we don't need, nmigen
default reset values are all zero (or, you can pass in the reset value
you want, on the "Signal"), the s_in_* and s_out_* stuff i already got
rid of...  i'm just going through the class looking at fsm_state to
see what the default reset value for that is (i *think* it's the first
state...)

l.

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 15c7210..599a5d0 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -344,13 +344,11 @@ class FPADD:
             with m.State("put_z"):
               m.next = "get_a"
               m.d.sync += [
-                  s_out_z_stb.eq(1),
-                  s_out_z.eq(z)
+                  self.out_z_stb.eq(1),
+                  self.out_z.eq(z.v)
               ]
-              with m.If(s_out_z_stb & out_z_ack):
-                  m.d.sync += [
-                  s_out_z_stb.eq(0)
-                  ]
+              with m.If(self.out_z_stb & self.out_z_ack):
+                  m.d.sync += self.out_z_stb.eq(0)

         return m