[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Thu, Feb 14, 2019 at 7:53 AM Aleksandar Kostovic
<alexandar.kostovic at gmail.com> wrote:
>
> Okay caught up to everything now. I see the mistake I did. Doing add_0 part
> now.

 got it.  cleanup below (committed already).

* in python, the level of indentation is critically important.  (and,
always use 4 spaces).
* for clarity, the members in the list (m.d.sync += block) is also
indented, and again for clarity the closing ] is also lined up.  this
isn't strictly necessary, it just looks better
* i added some comments so we can see what the heck is going on.


 -            with m.State("add_0"):
-              m.next = "add_1"
-              m.d.sync += z_e.eq(a_e)
-              with m.If(a_s == b_s):
-                m.d.sync += [
-                tot.eq(a_m + b_m),
-                z_s.eq(a_s)]
-              with m.Else(a_m >= b_m):
-                m.d.sync += [
-                tot.eq(a_m - b_m),
-                z_s.eq(a_s)]
-              with m.Else():
-                m.sync += [
-                tot.eq(b_m - a_m),
-                z_s.eq(b_s)]
+                # First stage of add
+                with m.State("add_0"):
+                    m.next = "add_1"
+                    m.d.sync += z_e.eq(a_e)
+                    with m.If(a_s == b_s):
+                        m.d.sync += [
+                            tot.eq(a_m + b_m),
+                            z_s.eq(a_s)
+                        ]
+                    with m.Else(a_m >= b_m):
+                        m.d.sync += [
+                            tot.eq(a_m - b_m),
+                            z_s.eq(a_s)
+                        ]
+                    with m.Else():
+                        m.sync += [
+                            tot.eq(b_m - a_m),
+                            z_s.eq(b_s)
+                    ]