[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Tuesday, February 12, 2019, Aleksandar Kostovic <
alexandar.kostovic at gmail.com> wrote:

> Thanks for clarification Jacob! :)
>
> Floating point is definitely tougher than I thought...
>
> Side question to everyone: Why don't we use something off the shelf and
> ready like berekely hardfloat? Yes, its scala/chisel but it can be
> converted to Verilog.


The resultant verilog is completely unreadable. It's done as a state
machine, going via Scala, instead of being language translated.

Hand editing of the resultant verilog would be insane, and if we needed
some changes we would be forced to learn Chisel.  Which was already
evaluated and found to be user hostile.

Also the hardfloat library is not complete.

L.


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