[libre-riscv-dev] IEEE754 FPU

[Jacob Lifshay]

On Tue, Feb 12, 2019, 02:01 Aleksandar Kostovic <
alexandar.kostovic at gmail.com> wrote:

> Okay so this is how I get it so far:
>
> Let's start with the number itself.
>
> |   sign  |    exponent  | fraction |
> -----------------------------------------
> |   1bit   |      8 bits      |  23bits  |
> -----------------------------------------
> |    31    | 30          23 | 22      0 |
>
> That's for single precision - 32 bit.
>
> Now let's talk about how sign number is determined. To my understanding
> sign is 0 if the number is positive(example 0.12345) and 1 in the number is
> negative(example -0.12345). When we need to add two floating point numbers,
> two sign's are just added using the XOR gate. If both are 0 or if both are
> 1 then the output is 0. Else it's 1.
>
that's all fmul, not fadd.
fadd has these cases for a + b:
a.sign == b.sign: use a.sign if a or b aren't zero, otherwise, use rounding
rules to get +0 or -0.
a.sign != b.sign: if fabs(a) > fabs(b) then use a.sign, else if fabs(a) <
fabs(b), then use b.sign, else follow rounding rules to get +0 or -0.

>
> What I don't yet understand are exponent and fraction. investigating that
> now. Also i found this FADD hardware implementation diagram:
>
diagram is for fmul, fadd doesn't need a multiplier and has to check
mantissa for sign.

>
>
> On Tue, Feb 12, 2019 at 10:04 AM Luke Kenneth Casson Leighton <
> lkcl at lkcl.net>
> wrote:
>
> > https://steve.hollasch.net/cgindex/coding/ieeefloat.html
> >
> > found a useful resource.
> > l.
> > On Tue, Feb 12, 2019 at 5:24 AM Luke Kenneth Casson Leighton
> > <lkcl at lkcl.net> wrote:
> > >
> > > and this.  i like rudi, he's cool.
> > > https://opencores.org/projects/fpu
> >
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