[libre-riscv-dev] OpenPiton parallelism and some links

[oajhfappp at firemail.cc]

First of all, thanks for everyone working on this project.
I don't know the technical details, but I really appreciate the efforts.

The Princeton University has a project called OpenPiton[1]. It's a
open source manycore processor. Originally based on OpenSPARC, but
some people ported some parts to work with RISC-V (see Ariane[2] and 
JuxtaPiton[3]).
Other projects from PULP also explores parallelism, such as bigPULP[4].

I thought maybe Simple-V could explore the parallel mechanism from these 
projects?
Or the caching mechanism?

Also, there's some exciting work being done on HDL (Clash[5] and BSV[6]) 
and on
open sourcing FPGA's workflow (see Symbiflow[7], Nextpnr[8], and 
nMigen[9] for
software and TinyFPGA[10], Radiona ULX3S[11] and Fomu[12] for hardware).

Hope some of these can be useful.



[1] http://parallel.princeton.edu/openpiton
[2] 
https://github.com/pulp-platform/ariane#preliminary-support-for-openpiton-cache-system
[3] https://arxiv.org/abs/1811.08091
[4] https://github.com/pulp-platform/bigpulp
[5] https://clash-lang.org/
[6] https://github.com/rsnikhil/Bluespec_BSV_Formal_Semantics
[7] https://symbiflow.github.io/
[8] https://github.com/YosysHQ/nextpnr
[9] https://github.com/m-labs/nmigen
[10] https://tinyfpga.com
[11] https://github.com/emard/ulx3s
[12] https://www.crowdsupply.com/sutajio-kosagi/fomu