[libre-riscv-dev] Divider pipeline structure

[Jacob Lifshay]

I propose having a radix-4 pipelined div/rem/sqrt/rsqrt unit with 16 stages
(plus a few for fp rounding and misc stuff) that is 64 bits wide and can be
partitioned into 2x32, 4x16, and 8x8 with the plan being that it can be
shared between 2 or 4 cores and would support 64-bit operations by passing
through the pipeline twice?
It would implement:
- div/rem for i8, i16, i32, and i64
- fdiv/fsqrt/frsqrt for f16, f32, and f64
- maybe fmod/frem for f16, f32, and f64

If needed, we could have sqrt/rsqrt be radix-2 and take 2 trips through the
pipeline for fp32, 1 for fp16, and 4 for fp64.

If shared between 4 cores, it would still have a 32-bit throughput of 1/2
operation per clock per core, which is sufficient.

For scheduling, it would have a 2-bit counter clocked by the core clock:
00: core 0 can start an operation
01: core 1 can start an operation
10: core 2 can start an operation
11: core 3 can start an operation

If a core doesn't need to start an operation in a particular cycle, it
starts a nop.

Not skipping any core prevents one core from detecting when another core is
issuing an operation, plugging that spectre leak.

Not splitting a execution slot into 2 separate 32-bit slots prevents a
different core from detecting that 64-bit operations were executed.

Thoughts?

Jacob



On Fri, Feb 1, 2019, 16:47 Luke Kenneth Casson Leighton <lkcl at lkcl.net
wrote:

> On Friday, February 1, 2019, Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> >
> > >
> > >  ermm... ermermerm....  input is 32 bits, result is 16 bits.
> > > therefore 16 bits *if the compare is done 1 bit at a time*.
> > >
> > You still need 32-bits for cases like 0x5000_0000 / 3.
>
>
> Oh, sorry: only 16 steps. Yes result would be 32bit.
>
> Might be ok to pipeline.
>
>
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