[libre-riscv-dev] Libre RISC-V Requirements Specification document

[Jacob Lifshay]

On Thu, Jan 10, 2019 at 5:05 AM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Thu, Jan 10, 2019 at 12:39 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > > > We would run 2 iterations of the lower loop per pipeline stage since
> that
> > > > matches what you need for radix-4 division. The pipeline would be
> approx
> > > 16
> > > > stages long.
> > >
> > >  only 8 stages if you have 3 parallel comparators and do 2 bits at a
> time.
> > >
> > no, 16 since there's 2 bits/stage and you need 32 bits
>
>  ermm... ermermerm....  input is 32 bits, result is 16 bits.
> therefore 16 bits *if the compare is done 1 bit at a time*.
>
You still need 32-bits for cases like 0x5000_0000 / 3.

>
>  i was referring to an augmented version of the algorithm where the
> compare phase takes *two* bits (i.e. does the operation in Base 4).
> this requires 3 parallel comparators.
>
Yup. I was thinking of packing 2 radix-2 division steps into a single
pipeline stage, but your method is faster (higher clock rate) and uses more
logic per-stage (3 subtractors, 1 4-input mux) than what I was thinking of
(2 subtractors, 2 2-input muxes). Note that you can combine the compare and
subtract into a single subtract, checking the carry out, since, if it
wraps, you don't need the result of subtraction.

Jacob