[libre-riscv-dev] VBLOCK, reducing context size: use SVP format

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Aug 31 21:30:41 BST 2019

I have been concerned about the setup cost of SVOrig enough to create
VBLOCK, however I think we can do better.

It occurred to me that the problem is the five bits needed to identify the
register to vectorise/predicate/swizzle.

Even the 8 bit format is too long.  RVV solves this by having a way to
specify some prearranged formats, as a bitfield.

So what could be done instead? What format is compact and covers up to 4
registers, and predication?

SVPrefix of course!

The only question is, how to get it to apply to multiple instructions, and
the answer is very simple: pick that information up from the very first
instruction in the VBLOCK.

This is highly likely to work because the destination register is likely to
be used as the src register in subsequent instructions.

In theory we could have *two* SVPrefixes (one optional), the second
applying to the second instruction and carrying its context forward across
multiple opcodes.

Another bit may specify that the 64 bit SVP format is to be used.

This is highly efficient because only 32 bits are needed to cover between
48 and 160 bits worth of instruction space.

That's 3 RVC to 10 RVC, or 1.5 to 5 OP32.  Only needing 32 bits to specify
the Vector Context!

Which at this point leaves me wondering if the other format is worth
reserving for a future iteration.

Thoughts appreciated as this is (another) major change to SV.


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