[libre-riscv-dev] [isa-dev] SV / RVV, marking a register as VL.
luke.leighton at gmail.com
Fri Aug 30 11:25:50 BST 2019
Nowait... hang on... it's dead simple. There is no need for that instruction-decode-rewrite trick, because it's not the *contents* of the register pointed to by VL that is needed to be returned, it's the *pointer* that is needed to be returned by CSRR rd, VL.
[getting at the *contents* - well, um... it's already *in* the scalar register!]
That has no effect on the scalar regfile read dependencies at all (just a write dependency on rd).
That in turn means no stalls of the ALU(s) on CSRR rd, VL.
So the only thing that an implementation need do in order to have a little extra speed is to cache the contents of the-register-pointed-to-by-VL in latches, and for that register to be managed by absolutely standard register dependency hazard techniques, and for the latch to be simultaneously written whenever the pointed-to register is also updated in the register file.
That really is not very challenging, microarchitecturally, at all.
I think we will go ahead with this change to SV, given the benefits it brings by effectively allowing the full range of RISC-V arithmetic operations to be applied directly to VL, in addition to the savings on instruction count.
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