[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=132

--- Comment #34 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #32)

> > here's a simple example:
> > 
> > -        with m.If(self.i.product[-1]):
> > -            comb += p.eq(self.i.product)
> > -        with m.Else():
> > -            # get 1 bit of extra accuracy if the mantissa top bit is zero
> > -            comb += p.eq(self.i.product<<1)
> > -            comb += self.o.z.e.eq(self.i.z.e-1)
> > +        msb = Signal(reset_less=True)
> > +        e = self.o.z.e
> > +        comb += msb.eq(self.i.product[-1])
> > +        comb += p.eq(Mux(msb, self.i.product, self.i.product<<1))
> > +        comb += e.eq(Mux(msb, self.i.z.e, self.i.z.e-1))
> > 
> > that would do alright, wouldn't it? 
> 
> that looks fine to me.

yeh.  oh, except i realised: arrays.  the next bit of the code is as follows:

        mw = self.o.z.m_width
        comb += [
            self.o.z.m.eq(p[mw+2:]),            # mantissa
            self.o.of.m0.eq(p[mw+2]),           # copy of LSB
            self.o.of.guard.eq(p[mw+1]),        # guard
            self.o.of.round_bit.eq(p[mw]),      # round
            self.o.of.sticky.eq(p[0:mw].bool()) # sticky
        ]

the assumption here is that the mantissa width is a fixed parameter.

we'll need a P-variant of "Part" which takes a *list* of partition-selectable
widths/offsets - is that making any sense?

this is going to be quite intrusive, however, ultimately, i think if we
tried to write an "explicit" partitioned version of this code (with for-loops
etc.) it would quickly become not just unreadable but also apparent that
the process is extremely regular and monotonous.

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